The present invention relates to a semiconductor integrated circuit device and to a technique for manufacturing the same. More particularly, the invention is concerned with a technique that is applicable to the fabrication of a semiconductor integrated circuit device having wiring which is formed by burying a conductive film in a wiring-forming groove formed in an insulator.
With improvement in the integration level of elements in a semiconductor integrated circuit device and reduction in size of a semiconductor chip, the wiring which constitutes the semiconductor integrated circuit device is becoming more and more fine and multi-layered. Particularly, in a semiconductor integrated circuit device of a logic type having a multi-layer wiring structure, a wiring delay is one dominant factor of the signal delay in the whole of the semiconductor integrated circuit device. The speed of a signal traveling through the wiring is proportional to both the wiring resistance and the wiring capacitance, and so, for correcting the wiring delay, it is important that both the wiring resistance and the wiring capacitance be decreased.
For decreasing the wiring resistance, the application of a damascene method using a copper material (copper (Cu) or a copper alloy) as a wiring material is being promoted. According to this method, a wiring groove or a connection hole is formed in an insulating film, then a wiring-forming or plug-forming conductive film is deposited on a main surface of a semiconductor substrate, and the conductive film present in other areas than the wiring groove or connection hole is removed by a chemical mechanical polishing (CMP) method, thereby to form buried wiring in the wiring groove or to form a plug in the connection hole. This method is suitable particularly for forming buried wiring using a copper-based conductive material for which microetching is difficult.
As a practical application of the damascene method, there is a dual-damascene method. According to this method, a connection hole for effecting connection between a wiring-forming groove (hereinafter referred simply to as a “wiring groove”) and underlying wiring is formed in an insulating film, then a wiring-forming conductive film is deposited on a main surface of a semiconductor substrate, further, the conductive film is removed by CMP in other areas than the groove so as to form buried wiring in the wiring groove, and a plug is formed within the connection hole. According to this method, especially in the manufacture of a semiconductor integrated circuit having a multi-layer interconnection structure, it is possible to reduce the number of manufacturing steps and reduce the wiring cost.
A wiring-forming technique using such a damascene method is disclosed, for example, in Japanese Unexamined Patent Publication No. Hei 10 (1998)-135153.
In Japanese Unexamined Patent Publication No. 2001-118922, in connection with a semiconductor device having buried wiring and a connection hole, the buried wiring comprising a conductive barrier film formed of a refractory metal or a refractory metal nitride and a main conductive layer formed of Cu, Cu alloy, Ag (silver), or Ag alloy, the connection hole being formed in an insulating film which is deposited on the buried wiring and which reaches an upper surface of the buried wiring, there is disclosed a technique wherein the connection hole has a bottom of a size almost equal to the size which covers the width of the buried wiring, and a multi-layer film of the same layer structure as that of the buried wiring is buried in the connection hole to form a plug, whereby the expansion of a void formed by an electromigration phenomenon at the plug-buried wiring boundary superior in adhesion is prevented.